# Errors: 0, Warnings: 0
# Compile of array_DEFINITION_4Kx16bit.VHD was successful.
# Errors: 0, Warnings: 0
# Compile of MODULE_RAM.VHD was successful.
# Errors: 0, Warnings: 0
# Compile of TEST_BENCH_RAM.VHD was successful.
vsim work.test_bench
# vsim work.test_bench 
# Start time: 17:28:52 on Jan 08,2026
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading synopsys.attributes
# Loading ieee.std_logic_misc(body)
# Loading ieee.std_logic_textio(body)
# Loading work.test_bench(sim)
# Loading work.types
# Loading work.module_ram(rtl)
do E:/work_QUESTA/JapanLogicDesign/RAM_TEST/wave_TEST_BENCH_RAM_20260108.do
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
run -all
# ** Failure:     <<<<<<<<<< END : The simulation was successful >>>>>>>>>>
#    Time: 1 us  Iteration: 1  Process: /test_bench/line__107 File: E:/work_QUESTA/JapanLogicDesign/RAM_TEST/TEST_BENCH_RAM.VHD
# Break in Process line__107 at E:/work_QUESTA/JapanLogicDesign/RAM_TEST/TEST_BENCH_RAM.VHD line 211
write format wave -window .main_pane.wave.interior.cs.body.pw.wf E:/work_QUESTA/JapanLogicDesign/RAM_TEST/wave_TEST_BENCH_RAM_20260108.do
quit
# End time: 17:29:16 on Jan 08,2026, Elapsed time: 0:00:24
# Errors: 1, Warnings: 1
