m255
K4
z2
!s11e vcom 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
dE:/intelFPGA/20.1
Emodule_ram
Z0 w1767858887
Z1 DPx4 work 5 types 0 22 5JdIaXUcSU4RhJXdH<0^f0
Z2 DPx4 ieee 18 std_logic_unsigned 0 22 ;eZjO2D4ZDz<]0>8AL<ne1
Z3 DPx4 ieee 15 std_logic_arith 0 22 [G314=:2zXJ`VORJe1J@Z1
Z4 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z5 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
!i122 118
Z6 dE:/work_QUESTA/JapanLogicDesign/RAM_TEST
Z7 8E:/work_QUESTA/JapanLogicDesign/RAM_TEST/MODULE_RAM.VHD
Z8 FE:/work_QUESTA/JapanLogicDesign/RAM_TEST/MODULE_RAM.VHD
l0
L30 1
VUg0ik]fkS]FT0J0`UHX9I2
!s100 ]7TKI7AZOgj3gZ:bkd7Rc3
Z9 OV;C;2020.1;71
32
Z10 !s110 1767860929
!i10b 1
Z11 !s108 1767860929.000000
Z12 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/RAM_TEST/MODULE_RAM.VHD|
Z13 !s107 E:/work_QUESTA/JapanLogicDesign/RAM_TEST/MODULE_RAM.VHD|
!i113 1
Z14 o-work work -2002 -explicit
Z15 tExplicit 1 CvgOpt 0
Artl
R1
R2
R3
R4
R5
DEx4 work 10 module_ram 0 22 Ug0ik]fkS]FT0J0`UHX9I2
!i122 118
l55
L42 58
VLdN?=hEXF08TT<;KIhIPo2
!s100 ATebRN<P3:4iT10<m?cI13
R9
32
R10
!i10b 1
R11
R12
R13
!i113 1
R14
R15
Etest_bench
Z16 w1767860695
Z17 DPx4 ieee 16 std_logic_textio 0 22 ^l:n6VFdg74Q?CKDhjD]D3
Z18 DPx8 synopsys 10 attributes 0 22 dc>JdEHRM@6GGENe5bZ?D1
Z19 DPx4 ieee 14 std_logic_misc 0 22 dN]HY6l5ohPcZ:TaC@B;53
R2
R3
R4
R5
!i122 119
R6
Z20 8E:/work_QUESTA/JapanLogicDesign/RAM_TEST/TEST_BENCH_RAM.VHD
Z21 FE:/work_QUESTA/JapanLogicDesign/RAM_TEST/TEST_BENCH_RAM.VHD
l0
L34 1
Vk`4f?k3lR4mN@0aRadBiY0
!s100 lzN:6=QFMan`=3hKM;A>Z3
R9
32
R10
!i10b 1
R11
Z22 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/RAM_TEST/TEST_BENCH_RAM.VHD|
Z23 !s107 E:/work_QUESTA/JapanLogicDesign/RAM_TEST/TEST_BENCH_RAM.VHD|
!i113 1
R14
R15
Asim
R17
R18
R19
R2
R3
R4
R5
Z24 DEx4 work 10 test_bench 0 22 k`4f?k3lR4mN@0aRadBiY0
!i122 119
l80
Z25 L37 183
Z26 VW:J@BdE<UGP5zI>^g<ZQI1
Z27 !s100 Nn:MQ6C7d5T9XN<3BW8gK2
R9
32
R10
!i10b 1
R11
R22
R23
!i113 1
R14
R15
Ptypes
R4
R5
!i122 117
w1764280438
R6
8E:/work_QUESTA/JapanLogicDesign/RAM_TEST/array_DEFINITION_4Kx16bit.VHD
FE:/work_QUESTA/JapanLogicDesign/RAM_TEST/array_DEFINITION_4Kx16bit.VHD
l0
L22 1
V5JdIaXUcSU4RhJXdH<0^f0
!s100 BFB6`o0PBN7E9CePd7nN10
R9
32
R10
!i10b 1
R11
!s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/RAM_TEST/array_DEFINITION_4Kx16bit.VHD|
!s107 E:/work_QUESTA/JapanLogicDesign/RAM_TEST/array_DEFINITION_4Kx16bit.VHD|
!i113 1
R14
R15
