m255
K4
z2
!s11e MIXED_VERSIONS
13
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cModel Technology
dC:/intelFPGA/20.1
Emodule_uart_8_bit
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!i122 318
Z5 dE:/work_QUESTA/JapanLogicDesign/UART_8_bit
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!s100 L`HkTBc1<f1fhQ`<2ddTd0
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!i10b 1
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!i113 1
Z13 o-work work -2002 -explicit
Z14 tExplicit 1 CvgOpt 0
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R1
R2
R3
R4
DEx4 work 17 module_uart_8_bit 0 22 JWLhPhUSTMb`ndJc<P8ia2
!i122 318
l116
L66 505
Vo^Vo4VzQ9RDmcI;:oJfm<2
!s100 XQaMVh:cF2;G62MYLh8g<0
R8
32
R9
!i10b 1
R10
R11
R12
!i113 1
R13
R14
Emodule_uart_n_bit
Z15 w1753797039
R1
R2
R3
R4
!i122 82
R5
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l0
L41 1
VJ6b[9;3kNTGo=dETm0Rm01
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R8
32
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!i113 1
R13
R14
Artl
R1
R2
R3
R4
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!i122 82
l117
L68 482
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!s100 TWQoMGB<U6]GVi6g_>;Fz1
R8
32
R18
!i10b 1
R19
R20
R21
!i113 1
R13
R14
Esim_module_uart_8_bit
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R1
R2
R3
R4
!i122 320
R5
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32
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!i113 1
R13
R14
Artl
R1
R2
R3
R4
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!i122 320
l103
Z28 L54 481
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R8
32
R9
!i10b 1
R10
R25
R26
!i113 1
R13
R14
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R1
R2
R3
R4
!i122 319
R5
Z35 8E:/work_QUESTA/JapanLogicDesign/UART_8_bit/TEST_BENCH_UART_8_bit.VHD
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32
R9
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R10
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!i113 1
R13
R14
Asim
R32
R33
R34
R1
R2
R3
R4
DEx4 work 10 test_bench 0 22 WYhoJDl;Jl2MO@]:<9nII3
!i122 319
l131
L38 607
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!s100 i_f4K1ig=IIIhSjO3eDXh0
R8
32
R9
!i10b 1
R10
R37
R38
!i113 1
R13
R14
