ESC[2JESC[0mESC[1;1HESC[?25lESC[36mESC[7m  LOGIC_ANALYZER Ver 1.0  Japan Logic Design [50MHz]  ESC[0m  TRIG:CH00,RISE,CONT  DIV:20nS 


ESC[0m200nS ---|---------|---------|---------|---------|---------|---------|---------|---------|---------|------


ESC[37m                                       T 


ESC[32mESC[7m CH00 ESC[27m~~~~~~~~_________________________~~~~~~~~~~~~~~~~~~~~~~~~~_________________________~~~~~~~~~~~~~~~~~


ESC[37m                                       | 


ESC[33m CH01 ~~~~____~~~~~____~~~~____~~~~____~~~~~____~~~~____~~~~____~~~~~____~~~~____~~~~____~~~~~____~~~~____

