m255
K4
z2
!s11e MIXED_VERSIONS
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
dE:/work_QUESTA/SLG_450_ONTIME_EXTEND
Eclk_wiz_0
Z0 w1768228569
Z1 DPx4 ieee 18 std_logic_unsigned 0 22 ;eZjO2D4ZDz<]0>8AL<ne1
Z2 DPx4 ieee 15 std_logic_arith 0 22 [G314=:2zXJ`VORJe1J@Z1
Z3 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z4 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
!i122 3212
Z5 dE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER
Z6 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/clk_wiz_0_DUMMY.vhd
Z7 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/clk_wiz_0_DUMMY.vhd
l0
Z8 L25 1
VzFNJd42S^^c<:3]AGHKed3
!s100 YXTIh8R9HMKU5I52k9Pl21
Z9 OV;C;2020.1;71
32
Z10 !s110 1769959610
!i10b 1
Z11 !s108 1769959610.000000
Z12 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/clk_wiz_0_DUMMY.vhd|
Z13 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/clk_wiz_0_DUMMY.vhd|
!i113 1
Z14 o-work work -2002 -explicit
Z15 tExplicit 1 CvgOpt 0
Artl
R1
R2
R3
R4
DEx4 work 9 clk_wiz_0 0 22 zFNJd42S^^c<:3]AGHKed3
!i122 3212
l43
L34 33
VDAViaN4OI^;FVn2d[hcLS0
!s100 :QkBa0T=`NKc8K_KHS>9U1
R9
32
R10
!i10b 1
R11
R12
R13
!i113 1
R14
R15
Ecommand_module
Z16 w1769958242
R1
R2
R3
R4
!i122 3223
R5
Z17 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/COMMAND_MODULE.vhd
Z18 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/COMMAND_MODULE.vhd
l0
R8
VZVM6]Q6kWcV4SFmC4LCHQ2
!s100 TaVSBd`K3HG@5LhzY?<F51
R9
32
Z19 !s110 1769959613
!i10b 1
Z20 !s108 1769959613.000000
Z21 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/COMMAND_MODULE.vhd|
Z22 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/COMMAND_MODULE.vhd|
!i113 1
R14
R15
Artl
R1
R2
R3
R4
DEx4 work 14 command_module 0 22 ZVM6]Q6kWcV4SFmC4LCHQ2
!i122 3223
l71
L47 173
V[9aFO[?`cB3l]2OKPkK8K0
!s100 BZWh37jXL>>JB5dHCkX4a0
R9
32
R19
!i10b 1
R20
R21
R22
!i113 1
R14
R15
Eled_blink
Z23 w1766779954
R1
R2
R3
R4
!i122 3213
R5
Z24 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/LED_BLINK.vhd
Z25 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/LED_BLINK.vhd
l0
R8
Vcljb_2eNU`0>Oce6b2]7C2
!s100 m>4L5M@92dnQ8hA<D>lAH2
R9
32
Z26 !s110 1769959611
!i10b 1
R11
Z27 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/LED_BLINK.vhd|
Z28 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/LED_BLINK.vhd|
!i113 1
R14
R15
Artl
R1
R2
R3
R4
DEx4 work 9 led_blink 0 22 cljb_2eNU`0>Oce6b2]7C2
!i122 3213
l47
L36 61
V2LAg;<8M:H]RR8Pf`1PDk0
!s100 lSL7dGTWPH>Gf?7Xk4H4[0
R9
32
R26
!i10b 1
R11
R27
R28
!i113 1
R14
R15
Emessage_data_mem
Z29 w1767787673
Z30 DPx4 work 5 types 0 22 Rj21iA3??0VUD>U7cZ7ZA0
R1
R2
R3
R4
!i122 517
R5
Z31 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/MESSAGE_DATA_MEM.VHD
Z32 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/MESSAGE_DATA_MEM.VHD
l0
R8
Vf1^KBYH8CnLW;>6aWj];S3
!s100 J9H=eg38U5d;=GB^<TJ872
R9
32
Z33 !s110 1767874870
!i10b 1
Z34 !s108 1767874870.000000
Z35 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/MESSAGE_DATA_MEM.VHD|
Z36 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/MESSAGE_DATA_MEM.VHD|
!i113 1
R14
R15
Artl
R30
R1
R2
R3
R4
DEx4 work 16 message_data_mem 0 22 f1^KBYH8CnLW;>6aWj];S3
!i122 517
l53
L38 44
VobW0l>D8TdhPEQWAAcg4C0
!s100 :EOn;aoVRWMfff@5JL[:?3
R9
32
R33
!i10b 1
R34
R35
R36
!i113 1
R14
R15
Emodule_uart_8_bit
Z37 w1769546309
R1
R2
R3
R4
!i122 3214
R5
Z38 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/MODULE_UART_8_bit.VHD
Z39 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/MODULE_UART_8_bit.VHD
l0
L45 1
V8l9d55A4kALMQb>8KXodD1
!s100 JK30b6Vf>`<=e_GB^Q_gl2
R9
32
R26
!i10b 1
Z40 !s108 1769959611.000000
Z41 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/MODULE_UART_8_bit.VHD|
Z42 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/MODULE_UART_8_bit.VHD|
!i113 1
R14
R15
Artl
R1
R2
R3
R4
DEx4 work 17 module_uart_8_bit 0 22 8l9d55A4kALMQb>8KXodD1
!i122 3214
l114
L70 452
VD6MUij2<fZ2d8L0o;2QQh0
!s100 hL1T@dDQF<gVOF9hg7A?U3
R9
32
R26
!i10b 1
R40
R41
R42
!i113 1
R14
R15
Enoise_reduction
Z43 w1768736172
R1
R2
R3
R4
!i122 3215
R5
Z44 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/NOISE_REDUCTION.VHD
Z45 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/NOISE_REDUCTION.VHD
l0
L35 1
VP2lBj_:A52LGMHE@l?E^R2
!s100 NdR:9XjW9>IeDmKZ=<kNg2
R9
32
R26
!i10b 1
R40
Z46 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/NOISE_REDUCTION.VHD|
Z47 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/NOISE_REDUCTION.VHD|
!i113 1
R14
R15
Artl
R1
R2
R3
R4
DEx4 work 15 noise_reduction 0 22 P2lBj_:A52LGMHE@l?E^R2
!i122 3215
l65
L50 87
VF>RWM[zg^f_=3edUMO?Fh1
!s100 6<oO[e:F5U:@nk_6:6Gjz2
R9
32
R26
!i10b 1
R40
R46
R47
!i113 1
R14
R15
Esig_data_buffer
Z48 w1768914561
Z49 DPx4 work 5 types 0 22 Vkm@nl`=]6E08gfz@5C^O3
R1
R2
R3
R4
!i122 3219
R5
Z50 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIG_DATA_BUFFER.VHD
Z51 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIG_DATA_BUFFER.VHD
l0
R8
VHaQ^5hianQnVz64g9B^073
!s100 Sa?mWbACW9GW06Efgj_o^1
R9
32
Z52 !s110 1769959612
!i10b 1
Z53 !s108 1769959612.000000
Z54 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIG_DATA_BUFFER.VHD|
Z55 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIG_DATA_BUFFER.VHD|
!i113 1
R14
R15
Artl
R49
R1
R2
R3
R4
DEx4 work 15 sig_data_buffer 0 22 HaQ^5hianQnVz64g9B^073
!i122 3219
l47
Z56 L38 38
VA_ZacjOR4SK^[:Ro5[e<>3
!s100 :ckB:PMLFf6]2^gaPII=I2
R9
32
R52
!i10b 1
R53
R54
R55
!i113 1
R14
R15
Esim_dummy_c_founter
Z57 w1768096484
R1
R2
R3
R4
!i122 1932
R5
Z58 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIM_DUMMY_COUNTER.VHD
Z59 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIM_DUMMY_COUNTER.VHD
l0
L24 1
V7h@`OS2<2W;KZagKCna1D3
!s100 OKd0g;dh]f3G;LB`d:Qi50
R9
32
Z60 !s110 1768405923
!i10b 1
Z61 !s108 1768405923.000000
Z62 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIM_DUMMY_COUNTER.VHD|
Z63 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIM_DUMMY_COUNTER.VHD|
!i113 1
R14
R15
Artl
R1
R2
R3
R4
DEx4 work 19 sim_dummy_c_founter 0 22 7h@`OS2<2W;KZagKCna1D3
!i122 1932
l44
L34 37
VKX2Jb^bah5lZU0?9zbJOY0
!s100 BGF3n3jJE0<_FDG0=chMA0
R9
32
R60
!i10b 1
R61
R62
R63
!i113 1
R14
R15
Esim_module_uart_8_bit
Z64 w1768228410
R1
R2
R3
R4
!i122 3216
R5
Z65 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIM_MODULE_UART_8_bit.VHD
Z66 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIM_MODULE_UART_8_bit.VHD
l0
L28 1
V>eTdQNX0ViLM54=:WR0_M3
!s100 <DRjS^3`2N4mVkO2JAB<W1
R9
32
R26
!i10b 1
R40
Z67 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIM_MODULE_UART_8_bit.VHD|
Z68 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/SIM_MODULE_UART_8_bit.VHD|
!i113 1
R14
R15
Artl
R1
R2
R3
R4
DEx4 work 21 sim_module_uart_8_bit 0 22 >eTdQNX0ViLM54=:WR0_M3
!i122 3216
l101
L55 474
VBJ55YX5T;KOO:GgN^2JBQ1
!s100 `WZPII35?>J`0^2eOU<B50
R9
32
R26
!i10b 1
R40
R67
R68
!i113 1
R14
R15
Etest_bench
Z69 w1769549180
Z70 DPx4 ieee 16 std_logic_textio 0 22 ^l:n6VFdg74Q?CKDhjD]D3
R1
R2
R3
R4
!i122 3222
R5
Z71 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TEST_BENCH_TOP_FPGA.VHD
Z72 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TEST_BENCH_TOP_FPGA.VHD
l0
L27 1
V@jXG3Y40L6T1TjC_LKe?J2
!s100 Ui0UdUoJSWhWBXVZcfGKh0
R9
32
R19
!i10b 1
R20
Z73 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TEST_BENCH_TOP_FPGA.VHD|
Z74 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TEST_BENCH_TOP_FPGA.VHD|
!i113 1
R14
R15
Asim
R70
R1
R2
R3
R4
DEx4 work 10 test_bench 0 22 @jXG3Y40L6T1TjC_LKe?J2
!i122 3222
l109
L30 405
VY_C7LeZQi@kCLT]7EQYU50
!s100 eQhJMMaWd^K`A_92@YEFh2
R9
32
R19
!i10b 1
R20
R73
R74
!i113 1
R14
R15
Etitle_data_mem
Z75 w1769346753
R49
R1
R2
R3
R4
!i122 3221
R5
Z76 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TITLE_DATA_MEM.VHD
Z77 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TITLE_DATA_MEM.VHD
l0
R8
V9297UKLdQ`JP0J@lMRMn:0
!s100 ]TFV;feIif;D_XPhMO>ci3
R9
32
R52
!i10b 1
R53
Z78 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TITLE_DATA_MEM.VHD|
Z79 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TITLE_DATA_MEM.VHD|
!i113 1
R14
R15
Artl
R49
R1
R2
R3
R4
DEx4 work 14 title_data_mem 0 22 9297UKLdQ`JP0J@lMRMn:0
!i122 3221
l64
L36 49
VAVWAm3fXeKcBQJSmUkR7E3
!s100 RUOAOoS3R>A0ClQkGW02J2
R9
32
R52
!i10b 1
R53
R78
R79
!i113 1
R14
R15
Etop_a7_logic_analyzer
Z80 w1769958477
Z81 DPx4 ieee 11 numeric_std 0 22 aU^R8eGcicLcUFIaBQSL>3
R1
R2
R3
R4
!i122 3220
R5
Z82 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_A7_LOGIC_ANALYZER.vhd
Z83 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_A7_LOGIC_ANALYZER.vhd
l0
Z84 L34 1
V_MhZIeWJAnmEBCXUOme8d2
!s100 SB5lh@bIEPYJT6FAfVY[D0
R9
32
R52
!i10b 1
R53
Z85 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_A7_LOGIC_ANALYZER.vhd|
Z86 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_A7_LOGIC_ANALYZER.vhd|
!i113 1
R14
R15
Artl
R81
R1
R2
R3
R4
DEx4 work 21 top_a7_logic_analyzer 0 22 _MhZIeWJAnmEBCXUOme8d2
!i122 3220
l348
L47 1932
V:OS]]aiDQ;;;ED]nmfY8_3
!s100 V0f`_CgWghbgg:RLNc4mf0
R9
32
R52
!i10b 1
R53
R85
R86
!i113 1
R14
R15
Etop_a7_uart_term
Z87 w1767339210
R81
R1
R2
R3
R4
!i122 50
R5
Z88 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_A7_UART_TERM.vhd
Z89 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_A7_UART_TERM.vhd
l0
R84
V0_YS3z81ESc_N60fSnjHi3
!s100 UBC7Y]K2b:F[Iz;f39?YS0
R9
32
Z90 !s110 1767787680
!i10b 1
Z91 !s108 1767787680.000000
Z92 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_A7_UART_TERM.vhd|
Z93 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_A7_UART_TERM.vhd|
!i113 1
R14
R15
Artl
R81
R1
R2
R3
R4
DEx4 work 16 top_a7_uart_term 0 22 0_YS3z81ESc_N60fSnjHi3
!i122 50
l168
L48 352
V@m?IdQQ=QNQif>H7a6;AV0
!s100 b;fKdH@U_@W;Ele9gPj5H1
R9
32
R90
!i10b 1
R91
R92
R93
!i113 1
R14
R15
Etop_fpga
Z94 w1769959491
R1
R2
R3
R4
!i122 3224
R5
Z95 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_FPGA.vhd
Z96 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_FPGA.vhd
l0
R8
VEX6oj0V_Qi=Ih6UdL4L[=3
!s100 LNFPEg>1E9fbQ^hh?3Yd02
R9
32
R19
!i10b 1
R20
Z97 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_FPGA.vhd|
Z98 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/TOP_FPGA.vhd|
!i113 1
R14
R15
Artl
R1
R2
R3
R4
Z99 DEx4 work 8 top_fpga 0 22 EX6oj0V_Qi=Ih6UdL4L[=3
!i122 3224
l119
Z100 L41 197
Z101 VH8e[Mj5OL?ek2:2H4M4oh0
Z102 !s100 [deOE^fljT^P96b0[B0mC2
R9
32
R19
!i10b 1
R20
R97
R98
!i113 1
R14
R15
Ptypes
R3
R4
!i122 3217
w1768914544
R5
8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/array_DEFINITION.VHD
FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/array_DEFINITION.VHD
l0
L20 1
VVkm@nl`=]6E08gfz@5C^O3
!s100 l1ZaL?mJ??R5gbO@2C2U@1
R9
32
R26
!i10b 1
R40
!s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/array_DEFINITION.VHD|
!s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/array_DEFINITION.VHD|
!i113 1
R14
R15
Euart_command_module
Z103 w1768674134
R1
R2
R3
R4
!i122 2058
R5
Z104 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/UART_COMMAND_MODULE.vhd
Z105 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/UART_COMMAND_MODULE.vhd
l0
R8
VB?c>:FkTOc@TXb_jY896D3
!s100 h_2cTS;FjLJ0z_ogMhj0L2
R9
32
Z106 !s110 1768674137
!i10b 1
Z107 !s108 1768674137.000000
Z108 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/UART_COMMAND_MODULE.vhd|
Z109 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/UART_COMMAND_MODULE.vhd|
!i113 1
R14
R15
Artl
R1
R2
R3
R4
DEx4 work 19 uart_command_module 0 22 B?c>:FkTOc@TXb_jY896D3
!i122 2058
l58
L42 100
VlSIA@6g8BHKn?T8m>Blb[0
!s100 c<0]A5>QI05Pl]IP@ae5c0
R9
32
R106
!i10b 1
R107
R108
R109
!i113 1
R14
R15
Euart_send_buffer
Z110 w1768125678
R49
R1
R2
R3
R4
!i122 3218
R5
Z111 8E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/UART_SEND_BUFFER.VHD
Z112 FE:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/UART_SEND_BUFFER.VHD
l0
R8
VDaK548QbPMdg89S31a2U73
!s100 [BJl^4Nf^zL9[ZJG`PlMP2
R9
32
R52
!i10b 1
R40
Z113 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/UART_SEND_BUFFER.VHD|
Z114 !s107 E:/work_QUESTA/JapanLogicDesign/A7_LOGIC_ANALYZER/UART_SEND_BUFFER.VHD|
!i113 1
R14
R15
Artl
R49
R1
R2
R3
R4
DEx4 work 16 uart_send_buffer 0 22 DaK548QbPMdg89S31a2U73
!i122 3218
l47
R56
Ve4Uc=C@NT;:1VKIlCfj8T3
!s100 K9XRbncW4Y9Vg7GfVA]?J2
R9
32
R52
!i10b 1
R40
R113
R114
!i113 1
R14
R15
