m255
K4
z2
!s11e vcom 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
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cModel Technology
dC:/intelFPGA/20.1
Ebin_to_hex
w1770972467
!i122 1573
Z0 dE:/work_QUESTA/JapanLogicDesign/A7_XADC
Z1 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/UART_SEND_HEX.vhd
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l0
L46 1
VAn]^OY05I1VVJ?9EBUBK20
!s100 OQi[BnI86U`T9eVaH[F_[0
Z3 OV;C;2020.1;71
32
!s110 1770972473
!i10b 1
!s108 1770972473.000000
Z4 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/work_QUESTA/JapanLogicDesign/A7_XADC/UART_SEND_HEX.vhd|
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!i113 1
Z6 o-work work -2002 -explicit
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Eclk_wiz_0
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!i122 1615
R0
Z13 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/clk_wiz_0_DUMMY.vhd
Z14 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/clk_wiz_0_DUMMY.vhd
l0
Z15 L25 1
VzFNJd42S^^c<:3]AGHKed3
!s100 YXTIh8R9HMKU5I52k9Pl21
R3
32
Z16 !s110 1770974232
!i10b 1
Z17 !s108 1770974232.000000
Z18 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/clk_wiz_0_DUMMY.vhd|
Z19 !s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/clk_wiz_0_DUMMY.vhd|
!i113 1
R6
R7
Artl
R9
R10
R11
R12
DEx4 work 9 clk_wiz_0 0 22 zFNJd42S^^c<:3]AGHKed3
!i122 1615
l43
L34 33
VDAViaN4OI^;FVn2d[hcLS0
!s100 :QkBa0T=`NKc8K_KHS>9U1
R3
32
R16
!i10b 1
R17
R18
R19
!i113 1
R6
R7
Eled_blink
Z20 w1766779954
R9
R10
R11
R12
!i122 1616
R0
Z21 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/LED_BLINK.vhd
Z22 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/LED_BLINK.vhd
l0
R15
Vcljb_2eNU`0>Oce6b2]7C2
!s100 m>4L5M@92dnQ8hA<D>lAH2
R3
32
Z23 !s110 1770974233
!i10b 1
R17
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!i113 1
R6
R7
Artl
R9
R10
R11
R12
DEx4 work 9 led_blink 0 22 cljb_2eNU`0>Oce6b2]7C2
!i122 1616
l47
L36 61
V2LAg;<8M:H]RR8Pf`1PDk0
!s100 lSL7dGTWPH>Gf?7Xk4H4[0
R3
32
R23
!i10b 1
R17
R24
R25
!i113 1
R6
R7
Emessage_data_mem
Z26 w1767354897
Z27 DPx4 work 5 types 0 22 :33m_:VHdmYQT=c8gWm2j1
R9
R10
R11
R12
!i122 862
Z28 dE:/work_QUESTA/JapanLogicDesign/A7_UART_TERM
Z29 8E:/work_QUESTA/JapanLogicDesign/A7_UART_TERM/MESSAGE_DATA_MEM.VHD
Z30 FE:/work_QUESTA/JapanLogicDesign/A7_UART_TERM/MESSAGE_DATA_MEM.VHD
l0
L26 1
VbR;K[N2i4H8UaZV2OA0Sm0
!s100 5Dz[U2XQ0BbhGcTKDJEFk2
R3
32
Z31 !s110 1767354966
!i10b 1
Z32 !s108 1767354966.000000
Z33 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/work_QUESTA/JapanLogicDesign/A7_UART_TERM/MESSAGE_DATA_MEM.VHD|
Z34 !s107 E:/work_QUESTA/JapanLogicDesign/A7_UART_TERM/MESSAGE_DATA_MEM.VHD|
!i113 1
R6
R7
Artl
R27
R9
R10
R11
R12
DEx4 work 16 message_data_mem 0 22 bR;K[N2i4H8UaZV2OA0Sm0
!i122 862
l52
L39 42
Vf6jFGgd2[:RL=@L>WMFUc0
!s100 c1@fXRHC1]<LL6U1cO`:11
R3
32
R31
!i10b 1
R32
R33
R34
!i113 1
R6
R7
Emodule_uart_8_bit
Z35 w1769546309
R9
R10
R11
R12
!i122 1624
R0
Z36 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/MODULE_UART_8_bit.VHD
Z37 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/MODULE_UART_8_bit.VHD
l0
L45 1
V8l9d55A4kALMQb>8KXodD1
!s100 JK30b6Vf>`<=e_GB^Q_gl2
R3
32
Z38 !s110 1770974234
!i10b 1
Z39 !s108 1770974234.000000
Z40 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/MODULE_UART_8_bit.VHD|
Z41 !s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/MODULE_UART_8_bit.VHD|
!i113 1
R6
R7
Artl
R9
R10
R11
R12
DEx4 work 17 module_uart_8_bit 0 22 8l9d55A4kALMQb>8KXodD1
!i122 1624
l114
L70 452
VD6MUij2<fZ2d8L0o;2QQh0
!s100 hL1T@dDQF<gVOF9hg7A?U3
R3
32
R38
!i10b 1
R39
R40
R41
!i113 1
R6
R7
Emodule_xadc_drp
Z42 w1770886888
Z43 DPx4 work 5 types 0 22 VziBnL1zTiV8>?HQ`E0U@2
R9
R10
R11
R12
!i122 1621
R0
Z44 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/MODULE_XADC_DRP.VHD
Z45 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/MODULE_XADC_DRP.VHD
l0
L30 1
VTbf@9mMA`YX=;g`nj_Gba0
!s100 J<FUh@I7@DZek63WcZOTz1
R3
32
R23
!i10b 1
Z46 !s108 1770974233.000000
Z47 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/MODULE_XADC_DRP.VHD|
Z48 !s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/MODULE_XADC_DRP.VHD|
!i113 1
R6
R7
Artl
R43
R9
R10
R11
R12
DEx4 work 15 module_xadc_drp 0 22 Tbf@9mMA`YX=;g`nj_Gba0
!i122 1621
l64
L49 116
V7@FiKAMgVz=<B150B7;W21
!s100 mYmgARLD5d_:6@l;1_W141
R3
32
R23
!i10b 1
R46
R47
R48
!i113 1
R6
R7
Enoise_reduction
Z49 w1768736172
R9
R10
R11
R12
!i122 1617
R0
Z50 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/NOISE_REDUCTION.VHD
Z51 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/NOISE_REDUCTION.VHD
l0
L35 1
VP2lBj_:A52LGMHE@l?E^R2
!s100 NdR:9XjW9>IeDmKZ=<kNg2
R3
32
R23
!i10b 1
R46
Z52 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/NOISE_REDUCTION.VHD|
Z53 !s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/NOISE_REDUCTION.VHD|
!i113 1
R6
R7
Artl
R9
R10
R11
R12
DEx4 work 15 noise_reduction 0 22 P2lBj_:A52LGMHE@l?E^R2
!i122 1617
l65
L50 87
VF>RWM[zg^f_=3edUMO?Fh1
!s100 6<oO[e:F5U:@nk_6:6Gjz2
R3
32
R23
!i10b 1
R46
R52
R53
!i113 1
R6
R7
Ppkg
R43
R9
R10
R11
R12
!i122 1584
Z54 w1770973301
R0
R1
R2
l0
Z55 L29 1
VHNgcQ:XcD[T]kWgJlfnNQ0
!s100 15e6[RCT=c06FC>WXG4O@2
R3
32
b1
Z56 !s110 1770973304
!i10b 1
Z57 !s108 1770973304.000000
R4
R5
!i113 1
R6
R7
Bbody
DPx4 work 3 pkg 0 22 HNgcQ:XcD[T]kWgJlfnNQ0
R43
R9
R10
R11
R12
!i122 1584
l0
L33 1
V==n8Gd9[<_]j;CC5?4gn@3
!s100 >lX9l2[j`k9T2FI]zPSo52
R3
32
R56
!i10b 1
R57
R4
R5
!i113 1
R6
R7
Esim_module_uart_8_bit
Z58 w1768228410
R9
R10
R11
R12
!i122 1623
R0
Z59 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/SIM_MODULE_UART_8_bit.VHD
Z60 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/SIM_MODULE_UART_8_bit.VHD
l0
L28 1
V>eTdQNX0ViLM54=:WR0_M3
!s100 <DRjS^3`2N4mVkO2JAB<W1
R3
32
R38
!i10b 1
R39
Z61 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/SIM_MODULE_UART_8_bit.VHD|
Z62 !s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/SIM_MODULE_UART_8_bit.VHD|
!i113 1
R6
R7
Artl
R9
R10
R11
R12
DEx4 work 21 sim_module_uart_8_bit 0 22 >eTdQNX0ViLM54=:WR0_M3
!i122 1623
l101
L55 474
VBJ55YX5T;KOO:GgN^2JBQ1
!s100 `WZPII35?>J`0^2eOU<B50
R3
32
R38
!i10b 1
R39
R61
R62
!i113 1
R6
R7
Etest_bench
Z63 w1770871236
Z64 DPx4 ieee 16 std_logic_textio 0 22 ^l:n6VFdg74Q?CKDhjD]D3
Z65 DPx8 synopsys 10 attributes 0 22 dc>JdEHRM@6GGENe5bZ?D1
Z66 DPx4 ieee 14 std_logic_misc 0 22 dN]HY6l5ohPcZ:TaC@B;53
R9
R10
R11
R12
!i122 1618
R0
Z67 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/TEST_BENCH_A7_XADC.VHD
Z68 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/TEST_BENCH_A7_XADC.VHD
l0
R55
Vm]<FaMmAY]M;c5O=QQPI73
!s100 ;YLX3@26Pa5>@46OBcZ^O0
R3
32
R23
!i10b 1
R46
Z69 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/TEST_BENCH_A7_XADC.VHD|
Z70 !s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/TEST_BENCH_A7_XADC.VHD|
!i113 1
R6
R7
Asim
R64
R65
R66
R9
R10
R11
R12
DEx4 work 10 test_bench 0 22 m]<FaMmAY]M;c5O=QQPI73
!i122 1618
l126
L32 247
V<W`X]b;BagOh;]NT10_Ri0
!s100 05bE:<1Jme9F2<]D4KIoW2
R3
32
R23
!i10b 1
R46
R69
R70
!i113 1
R6
R7
Etop_a7_uart_term
Z71 w1767339210
Z72 DPx4 ieee 11 numeric_std 0 22 aU^R8eGcicLcUFIaBQSL>3
R9
R10
R11
R12
!i122 860
R28
Z73 8E:/work_QUESTA/JapanLogicDesign/A7_UART_TERM/TOP_A7_UART_TERM.vhd
Z74 FE:/work_QUESTA/JapanLogicDesign/A7_UART_TERM/TOP_A7_UART_TERM.vhd
l0
L34 1
V0_YS3z81ESc_N60fSnjHi3
!s100 UBC7Y]K2b:F[Iz;f39?YS0
R3
32
R31
!i10b 1
R32
Z75 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|E:/work_QUESTA/JapanLogicDesign/A7_UART_TERM/TOP_A7_UART_TERM.vhd|
Z76 !s107 E:/work_QUESTA/JapanLogicDesign/A7_UART_TERM/TOP_A7_UART_TERM.vhd|
!i113 1
R6
R7
Artl
R72
R9
R10
R11
R12
DEx4 work 16 top_a7_uart_term 0 22 0_YS3z81ESc_N60fSnjHi3
!i122 860
l168
L48 352
V@m?IdQQ=QNQif>H7a6;AV0
!s100 b;fKdH@U_@W;Ele9gPj5H1
R3
32
R31
!i10b 1
R32
R75
R76
!i113 1
R6
R7
Etop_fpga
Z77 w1770871915
R43
R9
R10
R11
R12
!i122 1622
R0
Z78 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/TOP_FPGA.vhd
Z79 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/TOP_FPGA.vhd
l0
Z80 L27 1
VVYgP>nog1@G_4i<TPh^BV2
!s100 fe6m@Y_`F?=Wcc4V>nL363
R3
32
R23
!i10b 1
R46
Z81 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/TOP_FPGA.vhd|
Z82 !s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/TOP_FPGA.vhd|
!i113 1
R6
R7
Artl
R43
R9
R10
R11
R12
DEx4 work 8 top_fpga 0 22 VYgP>nog1@G_4i<TPh^BV2
!i122 1622
l208
L54 424
VXd2f=5ITEj5;OLJ0jKdkS1
!s100 @VdIGKU3Rc<a7<3;Nc1f`1
R3
32
R23
!i10b 1
R46
R81
R82
!i113 1
R6
R7
Ptypes
R11
R12
!i122 1620
w1770869075
R0
8E:/work_QUESTA/JapanLogicDesign/A7_XADC/array_DEFINITION.VHD
FE:/work_QUESTA/JapanLogicDesign/A7_XADC/array_DEFINITION.VHD
l0
L20 1
VVziBnL1zTiV8>?HQ`E0U@2
!s100 =3gS[MdTM9:KGEB8P8i@@0
R3
32
R23
!i10b 1
R46
!s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/array_DEFINITION.VHD|
!s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/array_DEFINITION.VHD|
!i113 1
R6
R7
Euart_send_hex
Z83 w1770974219
R43
R9
R10
R11
R12
!i122 1625
R0
R1
R2
l0
R55
Vn>SYJiPlEP^lR7iRVH>ma0
!s100 2J7I85WUmZ?5Bm0P;0ok:1
R3
32
R38
!i10b 1
R39
Z84 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/UART_SEND_HEX.vhd|
R5
!i113 1
R6
R7
Artl
R43
R9
R10
R11
R12
Z85 DEx4 work 13 uart_send_hex 0 22 n>SYJiPlEP^lR7iRVH>ma0
!i122 1625
l128
Z86 L46 247
Z87 VilCRCKl9zk[3`[oPNnon>3
Z88 !s100 d]BGWo;T`T_oDh2MRNNmY2
R3
32
R38
!i10b 1
R39
R84
R5
!i113 1
R6
R7
Exadc_wiz_0
Z89 w1770869571
R43
R9
R10
R11
R12
!i122 1619
R0
Z90 8E:/work_QUESTA/JapanLogicDesign/A7_XADC/xadc_wiz_0.vhd
Z91 FE:/work_QUESTA/JapanLogicDesign/A7_XADC/xadc_wiz_0.vhd
l0
R80
VR16RR5=mKEMT=[4em786F2
!s100 7mJXQH_:Z9;g9=AI>a3YM0
R3
32
R23
!i10b 1
R46
Z92 !s90 -reportprogress|300|-work|work|-2002|-explicit|E:/work_QUESTA/JapanLogicDesign/A7_XADC/xadc_wiz_0.vhd|
Z93 !s107 E:/work_QUESTA/JapanLogicDesign/A7_XADC/xadc_wiz_0.vhd|
!i113 1
R6
R7
Artl
R43
R9
R10
R11
R12
DEx4 work 10 xadc_wiz_0 0 22 R16RR5=mKEMT=[4em786F2
!i122 1619
l76
L53 97
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!s100 T^KHhW]43V2c^3fdg5Pn@2
R3
32
R23
!i10b 1
R46
R92
R93
!i113 1
R6
R7
