xadc_wiz_0.vhd,vhdl,xil_defaultlib,../../../../MAIN_001.gen/sources_1/ip/xadc_wiz_0_1/xadc_wiz_0.vhd,incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"
glbl.v,Verilog,xil_defaultlib,glbl.v
